Instruction Pipelining

Instruction Pipelining

Imagine an assembly line in a factory - instead of building one car completely before starting the next, you break the process into stages and overlap them. That's exactly what instruction pipelining does for computer instructions!

The Basic Concept

Without pipelining, each instruction completes before the next one starts. With pipelining, multiple instructions are in different stages of execution simultaneously.

    Without Pipelining (Sequential)
    +---------------------------------------------+
    |  Time  |  Inst 1  |  Inst 2  |  Inst 3    |
    |--------|----------|----------|------------|
    |  T1    |  Fetch   |          |            |
    |  T2    |  Decode  |          |            |
    |  T3    |  Execute |          |            |
    |  T4    |  Write   |  Fetch   |            |
    |  T5    |          |  Decode  |            |
    |  T6    |          |  Execute |  Fetch     |
    |  T7    |          |  Write   |  Decode    |
    |  T8    |          |          |  Execute   |
    |  T9    |          |          |  Write     |
    +---------------------------------------------+
    Total: 9 clock cycles for 3 instructions
    
    With Pipelining (Overlapped)
    +---------------------------------------------+
    |  Time  |  Inst 1  |  Inst 2  |  Inst 3    |
    |--------|----------|----------|------------|
    |  T1    |  Fetch   |          |            |
    |  T2    |  Decode  |  Fetch   |            |
    |  T3    |  Execute |  Decode  |  Fetch     |
    |  T4    |  Write   |  Execute |  Decode    |
    |  T5    |          |  Write   |  Execute   |
    |  T6    |          |          |  Write     |
    +---------------------------------------------+
    Total: 6 clock cycles for 3 instructions

Classic 5-Stage Pipeline

The classic instruction pipeline has five stages:

1. Instruction Fetch (IF): Get instruction from memory
2. Instruction Decode (ID): Determine instruction type and read registers
3. Execute (EX): Perform ALU operation or calculate address
4. Memory Access (MEM): Read/write data memory if needed
5. Write Back (WB): Write results back to register file

Pipeline Hazards

Pipelining isn't perfect - three types of hazards can stall the pipeline:

    Types of Pipeline Hazards
    +---------------------------------------------+
    |                                             |
    |  1. Structural Hazards:                     |
    |     Hardware can't support two instructions |
    |     in same stage simultaneously           |
    |                                             |
    |  2. Data Hazards:                           |
    |     Instruction depends on result of       |
    |     previous instruction                   |
    |                                             |
    |  3. Control Hazards:                        |
    |     Branch instructions change the flow    |
    |     of execution                           |
    |                                             |
    +---------------------------------------------+

Modern CPUs use techniques like forwarding, branch prediction, and out-of-order execution to minimize these hazards.

Benefits of Pipelining

• Increased Throughput: More instructions completed per second
• Better Hardware Utilization: All parts of CPU are busy every clock cycle
• Higher Clock Speeds: Each stage is simpler and can run faster

The ideal speedup is equal to the number of pipeline stages, though real-world performance is lower due to hazards.